- He Tingbo, head of Huawei Technologies Co., Ltd.'s semiconductor business, announced at the 2026 IEEE International Conference on Circuits and Systems in Shanghai that they plan to produce high-end chips with transistor density equivalent to a 1.4-nanometer process by 2031 using a new Tao's Law and logic folding technology.
- This new technological path aims to replace traditional geometric scaling with time scaling, breaking the traditional economic and physical limits of advanced process miniaturization without ASML's extreme ultraviolet lithography equipment.
- The global chip market reacted sensitively to this news, with market funds closely watching whether TSMC's current approximately five-year technological lead will be marginally narrowed by the rise of non-traditional process paths.
Real-time Market Reaction and Technological Path
Following the announcement, valuations in the US and Asia-Pacific semiconductor sectors experienced marginal fluctuations. Huawei's announcement that it will successfully implement logic folding technology for the first time in its new Kirin smartphone chip, to be released in the fall of 2026, expanding the original single-layer design to a double-layer, enhancing transistor density and other metrics, has prompted the market to reprice the long-term certainty of the traditional semiconductor supply chain. If Huawei's time scaling path can be commercially validated in mass production without the physical limitations of ASML's most advanced high-end EUV equipment, it means that competitors in the advanced process market will no longer be solely constrained by specific countries and specific equipment manufacturers. The long-term capital expenditure plans of the wafer foundry sector and semiconductor equipment manufacturers may face pressure for revision.
Capital Expenditure and Process Bottleneck Breakthrough
According to Huawei's disclosed technology roadmap, its developed logic folding technology and Tao's Law achieve a leap in transistor density by systematically compressing signal propagation delay. If the yield of this process reaches a commercial critical point within the next five years, it means that the catch-up cycle of China's semiconductor industry in advanced processes may be shortened. If the cost benefits of traditional Moore's Law geometric scaling completely dissipate before the 1.4-nanometer node, TSMC's plan to mass-produce 1.4-nanometer chips by 2028 will face asymmetric challenges. Market traders are beginning to reassess the global supply premium of high-end AI chips, especially in filling the vacuum in the Chinese market after Nvidia's restrictions.
Marginal Changes in the Localization Process of the Supply Chain
Based on high-frequency data and policy evolution, Huawei has designed and mass-produced 381 chips over the past six years based on this law. This indicates that its localized solutions in the fields of smartphones and artificial intelligence computing have evolved from single-point breakthroughs to systematic evolution. Due to long-term multi-country export restrictions, Beijing's financial support and procurement tilt towards semiconductor autonomy will remain high. If foundry partners like SMIC successfully cooperate with this architecture to complete production line optimization in the coming years, the marginal revenue structure of the global semiconductor equipment sector will undergo asset restructuring, and the pricing power of traditional wafer foundry giants may gradually come under pressure.
